The present invention relates to an active matrix type liquid crystal display apparatus preferably applicable to a projection-type display system or a projector, and more particularly to an active matrix type liquid crystal display apparatus capable of suppressing a drive frequency in a row signal electrode drive circuit and realizing an excellent AC driving of the liquid crystal elements, thereby improving the quality in the liquid crystal video display. Furthermore, the present invention relates to an improvement of video display quality robust against adverse influence of the wiring resistance etc.
Conventionally, transmission-type liquid crystal display apparatuses are adopted in many of projection-type display systems and projectors. On the other hand, reflection-type liquid crystal display apparatuses have been recently used to attain a higher aperture rate under the severe requirement of high densification of pixels and also to realize higher resolution as well as higher brightness.
In both cases, improvement of the display quality and reduction of the costs are strictly required.
FIG. 8 shows a fundamental arrangement of a conventional active matrix type display apparatus employed in the transmission-type and reflection-type liquid crystal display apparatuses.
In FIG. 8, Di (i=1,2,3, - - - ) represents a plurality of row signal electrodes and Gj (j=1,2,3, - - - ) represents a plurality of line scanning electrodes. The row signal electrodes Di (i=1,2,3, - - - ) and the line scanning electrodes Gj (j=1,2,3, - - - ) are arranged in a matrix pattern on a substrate. An active element circuit, consisting of a switching transistor 1 and an auxiliary capacitor 2, is formed at respective intersections formed by the row signal electrodes Di and the line scanning electrodes Gj. A plane pixel electrode 3 is provided on each surface dissected by the row signal electrodes Di and the line scanning electrodes Gj. Each pixel electrode 3 is connected to a connecting point between the switching transistor 1 and the auxiliary capacitor 2 in each active element circuit. A liquid crystal orientation film (not shown) is provided on the upper surface of the pixel electrode 3.
The liquid crystal orientation film and a common electrode film 4 are provided on a glass substrate (not shown), which is positioned in a confronting relationship with the substrate for the above-described active elements. A liquid crystal 5 is sealed tightly in a clearance space between these opposed substrates, so as to form a light modulating section.
Each row signal electrode Di is driven by an analog switch 6-i connected to this row signal electrode Di. A plurality of analog switches 6-i (i=1,2,3, - - - ) are associated with a horizontal shift register 7 to form a row signal electrode drive circuit 8. Each line scanning electrode Gj is driven by a line scanning electrode drive circuit 9. The row signal electrode drive circuit 8 and the line scanning electrode drive circuit 9 are disposed along the sides of the light modulating section.
More specifically, in the row signal electrode drive circuit 8, the horizontal shift register 7 is activated in response to a horizontal reset signal (i.e., HRST) and a horizontal shift clock (i.e., HCLK) sent from a drive timing pulse generating circuit (not shown). The activated horizontal shift register 7 successively turns on and off analog switches 6-i (i=1,2,3, - - - ) to supply a video signal Sig of each horizontal scanning period to a corresponding row signal electrode Di.
The line scanning electrode drive circuit 9 is formed by a vertical shift register which is activated in response to a vertical reset signal (i.e., VRST) and a vertical shift clock (i.e., VCLK) entered from the drive timing pulse generating circuit (not shown). The activated vertical shift register successively applies a select pulse to each line scanning electrode Gj to successively turn on each switching transistor 1 for one horizontal scanning period.
Accordingly, the video signal supplied to the row signal electrode Di charges the auxiliary capacitor 2 via the switching transistor 1 connected to a currently selected line scanning electrode Gj. The electrical potential (i.e., the voltage) of the pixel electrode 3 varies in accordance with the charging of the auxiliary capacitor 2. Thus, each pixel region of the liquid crystal 5 is independently activated in response to the voltage of the pixel electrode 3 so as to realize a pixel-by-pixel modulation of the reading light irradiated to the light modulating section.
FIG. 9 shows the relationship between horizontal scanning signals (1,2,3, - - - ) included in the video signal Sig of the non-interlaced scanning type (i.e., the ordered scanning type) and application of the selection pulse to each line scanning electrode Gj (i=1,2,3, - - - N) in the line scanning electrode drive circuit 9.
As apparent from FIG. 9, to realize the AC driving of the liquid crystal element 5, the polarity of the video signal Sig is alternately inverted in synchronism with the start timing of each vertical scanning period (i.e., frame period) so that the video signal Sig has opposed electrical potentials with respect to a predetermined reference potential between two neighboring vertical scanning periods. Respective line scanning electrodes Gj (i=1,2,3, -) are successively turned on in response to the selection pulse corresponding to each horizontal scanning period. Each pixel signal is supplied to each row signal electrode Di by closing the corresponding analog switch 6-i during the turning-on duration of each line scanning electrode Gj.
As a result, the light modulating section forms the frame video at the end of each vertical scanning period, so as to obtain the projection light of the pixel-by-pixel modulated frame video.
As described above, the liquid crystal display apparatus forms the frame video based on the video signal Sig of the non-interlaced scanning type. In other words, it was difficult to realize the similar video display by performing the horizontal scanning of the video signal of the interlaced scanning type (i.e., the jump-over scanning type). This is because the AC driving of approximately 30 Hz is definitely necessary for activating the liquid crystal, as understood from FIG. 9 wherein the polarity of the video signal Sig is inverted in synchronism with the start timing of each vertical scanning period.
However, Japanese Patent No. 7-32473 (publication of the examined patent application) discloses a liquid crystal display apparatus capable of realizing a high-quality video display by using the video signal of the interlaced scanning type. According to this prior art, the activating method of the line scanning electrodes is characteristic.
FIG. 10 shows a fundamental arrangement of the liquid crystal display apparatus disclosed in Japanese Patent No. 7-32473. Both the light modulating section and the row signal electrode drive circuit 8 are formed in the same manner as those disclosed in FIG. 9. However, a line scanning electrode drive circuit 10 is formed by a vertical shift register whose stage number is approximately a half of the total display line number. Output terminals of the line scanning electrode drive circuit 10 are connected to the odd-number line scanning electrodes Gj (j=1,3,5, - - - ). There are a plurality of analog switches 11-p (p=1,2,3, - - --), each selectively connecting an even-number line scanning electrode Gj (j=2,4,6, - - - ) to one of two neighboring odd-number line scanning electrodes Gj (j=1,3,5, - - - ) in synchronism with the start timing of each field period.
According to this apparatus, the switching of the analog switch 11-p (p=1,2,3, - - - ) is performed in response to the video signal Sig of the interlaced scanning type. More specifically, a switching control signal O/E (i.e., odd/even field signal) is supplied to each analog switch 11-p in synchronism with the start timing of each field period. Each analog switch 11-p is connected to a stationary terminal "a" when the field is an odd-number field and connected to another stationary terminal "b" when the field is an even-number field. As shown in FIG. 11, in the odd-number field, the video signals (1,3,5, - - - ) of the odd-number horizontal lines are successively written to the pixel electrodes 3 of the corresponding odd-number lines as well as the next even-number lines. The video signal of each odd-number horizontal line is thus written to two pixel electrodes 3 of the corresponding odd-number line and the next even-number line. In the even-number field, the video signals (2,4,6, - - - ) of the even-number horizontal lines are successively written to the pixel electrodes 3 of the corresponding even-number lines as well as the next odd-number lines. The video signal of each even-number horizontal line is thus written to two pixel electrodes of the corresponding even-number line and the next odd-number line.
Accordingly, in the odd-number field, each odd-number line scanning electrode G.sub.j (=1,3,5, - - - ) and the next even-number line scanning electrode G.sub.i+ (j=1,3,5, - - - ) are combined as a set of two neighboring line scanning electrodes receiving the same video signal "j" (j=1,3,5, - - - ) of the odd-number horizontal line. In the even-number field, each even-number line scanning electrode G.sub.j (j=2,4,6, - - - ) and the next odd-number line scanning electrode G.sub.i+1 (j=2,4,6, - - - ) are combined as another set of two neighboring line scanning electrodes receiving the same video signal "j" (j=2,4,6, - - - ) of the even-number horizontal line. When compared between the odd-number field and the even-number field, the writing of the video signal is performed by shifting one line in the vertical direction.
Furthermore, to realize the AC driving of the liquid crystal element 5, the polarity of the video signal Sig is alternately inverted in synchronism with the start timing of every field period so that the video signal Sig has opposed electrical potentials with respect to a predetermined reference potential between two neighboring fields.
However, according to the active matrix type liquid crystal display apparatus shown in FIGS. 8 and 9, when the video signal Sig is supplied in accordance with the non-interlaced scanning, its horizontal frequency is relatively large compared with the video signal of the interlaced scanning type. The drive frequency of the row signal electrode drive circuit 8 increases correspondingly. This is disadvantageous especially when the liquid crystal display apparatus displays the high-quality video signal whose pixel number is large.
To reduce the substantial drive frequency, the horizontal line video signal may be modified into multi-phase parallel signals to process each signal in a divided horizontal shift register. However, increasing the phase number will require size-enlarged peripheral circuits. This will increase the manufacturing costs of hardware components.
On the other hand, according to the liquid crystal display apparatus shown in FIGS. 10 and 11, the video signal Sig is limited to the interlaced scanning type. Thus, this apparatus cannot be applied to the video signal of the non-interlaced scanning type.
Furthermore, in the above-described conventional liquid crystal display apparatuses, the line scanning electrodes Gj (j=1,2,3, - - - ) and the row signal electrodes Di (i=1,2,3, - - - ) are thin leads pattern printed on a substrate. Accordingly, they have a wiring resistance and a related stray capacitance.
FIG. 12 shows an equivalent circuit showing the line scanning electrode Gj connected to corresponding active elements of the pixel portions. In FIG. 12, Rg represents the wiring resistance and Cg represents a composite capacitance. In this case, the composite capacitance Cg includes the gate capacitance of the switching transistor 1 in addition to the stray capacitance of the lead. In view of the overall electric characteristics, the connecting circuit of the line scanning electrode Gj can be regarded as a RC distributed constant circuit.
When the active matrix circuit is formed on a monocrystalline silicon substrate or a glass substrate by a thin film process, the wiring of each line scanning electrode Gj is generally formed by the polycrystalline silicon process. The sheet resistance is generally in the range from 1 to 100 (.OMEGA..multidot.cm). When the liquid crystal display apparatus has an increased number of pixels, the wiring length is correspondingly increased. This significantly enlarges the ratio of the wiring length to the wiring width to a higher level where the influence of the wiring resistance is not negligible.
FIG. 13 shows a waveform of the select pulse applied to the line scanning electrode Gj shown in the equivalent circuit (FIG. 12). In FIG. 13, "P" represents the waveform of the select pulse at a portion located near the line scanning electrode drive circuit 10, and "Q" represents the waveform of the select pulse at a portion located far from the line scanning electrode drive circuit 10.
As understood from FIG. 13, the waveform of the select pulse becomes dull by the influence of the RC distributed constant circuit defined by the wiring resistance Rg and the composite capacitance Cg. The influence of the RC distributed constant circuit is roughly proportional to the distance from the output terminal of the line scanning electrode circuit 10. In the worst case, the peak level of the select pulse will be reduced by an amount of .DELTA.VG as shown in FIG. 13.
FIGS. 14A through 14C show the writing operation of the video signal to a "j" line pixel electrode 3. FIG. 14A shows the waveform of the video signal Sig supplied to the pixel electrode 3 connected to the "j" line scanning electrode Gj. The polarity of the video signal Sig is inverted at the intervals of the field period to realize the AC driving of the liquid crystal 5. FIG. 14B shows the waveform of the select pulse applied to the "j" line scanning electrode Gj. The switching transistor 1 is turned on during one horizontal scanning period where the select pulse is in a H-level. FIG. 14C shows the pixel voltage Vpix written to the pixel electrode 3 via the switching transistor 1. The writing operation is performed for one horizontal scanning period in response to the application of the select pulse to the corresponding line scanning electrode Gj.
To perform the writing operation, the charging or discharging of the auxiliary capacitor 2 and the liquid crystal 5 is controlled by the switching transistor 1. In this case, if the select pulse has a reduced peak level, it will be impossible to receive a sufficient amount of current from the switching transistor 1. The writing operation of the pixel signal cannot be satisfactorily performed during one horizontal scanning period.